;-*- Mode:Text -*-

; Stuff for Kent
; 7/18

;;;;;;;;;;;;;;;;

MD / VMA boxed bits:

(destinations)

vma-start-read (all cases)
	set MD_BOXED from IR:55, VMA_BOXED from IR:54.
vma-start-write
	set VMA_BOXED from IR:54, preserve MD_BOXED.
md-start-write
	set MD_BOXED from IR:55, VMA_BOXED from IR:54.
md
	set MD_BOXED from IR:55.
vma
	set VMA_BOXED from IR:54.

If a DEST to MD or VMA is aborted because the previous mem cycle was a write
and it hasn't reached the point at which it knows if it will trap or not,
the machine must be frozen (cache-miss style) at or before the DEST cycle
that would clobber MD or VMA, such that if the trap is not taken, the DEST is
still asserted and the instruction can be completed as if nothing happened.

The decision to freeze the machine because a write-in-progress is followed
by a DEST to VMA or MD may be as simple as decoding a write to any functional
destination.  It is required that if the trap is taken, the DEST to VMA or MD
is inhibited, so that the trap routine can read the old values of them.


The timing for writing MD_BOXED and VMA_BOXED can be the same as for
writing MD and VMA.

It is not necessary for MD_BOXED and VMA_BOXED to be writable
indirectly; they can be restored by writing "md" and "vma".
They should be readable through any kind of status register.

Note that the bits cannot be written indirectly with the output
of the P-board boxed-bit mux.

;;;;;;;;;;;;;;;;

example:

MD <- foo
VMA-start-write <- bar
no-op
VMA-start-read-early <- bletch

The -start-write cannot be immediately followed by the -start-read-early
because both be driving the DEST during the same cycle.

Assume that the VMA-start-write causes a page-fault or GC trap.
The VMA-start-write instruction completely normally.  The
VMA-start-read-early must be frozen at or before its DEST cycle,
until it is known whether or not the VMA-start-write will cause a trap.
If it does cause a trap, the VMA-start-read-early must be aborted
(trapped before it's commit point, with the early DEST inhibited)
so that it can be reexecuted normally after the trap is handled.
It is not necessary for the trap-on-write to abort the instruction
that caused it.

;;;;;;;;;;;;;;;;

If an instruction that did VMA-start-read-early is trapped for
any reason (in particular, a case in which the early-DEST write was
NOT inhibited), the memory (local or Nubus) cycle that is started
by the -start-read-early must be aborted before it affects any
nubus device, and also, the MD and MD_BOXED must not be clobbered.

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

Other stuff on memory board:

4-bit status register to read 4 wire-wrap posts, for ECO level.

3-bit LED output.

Nubus-slot-ID in a status register.

;;;;;;;;;;;;;;;;

;; added after first copy printed
;; changed after second copy printed

Two bits of state kept for traps caused by memory cycles.
During normal operation, the bits are set from the map, transport
and GC ram outputs after memory cycles have been started.
The bits should be readable in a status register, and must be
directly writable so that a trap routine can save and restore
the complete state of the MD and VMA registers, MD and VMA boxed-bits,
and RD_TRAP and WR_TRAP bits.

For example, if a trap is caused for a reason unrelated to the memory
system, and the memory system state is such that a vma-start-read was
done and the cycle is complete, but MD has not been referenced yet,
the trap routine must be able to save state, do arbitrary work
with MD and VMA, and then restore the MD and VMA state such that
when the aborted code reads MD, the original trap will be caused.


RD_TRAP:
	Bit that indicates if sourcing MD will cause a trap.
	Bit is set and cleared as a side-effect of starting memory cycles,
	and is also directly readable and writable from software.
RD_TREQ:
	Bit indicates that a trap is currently asserted because
	MD was sourced while RD_TRAP was set.  Bit is an input to
	trap logic, and is readable as a (read-only) status bit.
WR_TRAP:
	Bit indicates that a memory write has caused a page-fault or
	GC trap.  

RD_TRAP:
	Bit is set when starting a memory read, by VMA-START-READ or
	VMA-START-READ-EARLY, if the cycle causes the map / GC logic
	to assert the page-fault or trans-trap outputs.

	Bit is cleared when starting any memory read or write.

	Trap request is asserted during the cycle after a cycle
	in which MD is sourced and the RD_TRAP bit is set, such
	that the instruction that sourced MD is aborted.

	The RD_TRAP bit is also directly readable and writable (0 or 1)
	from software.  This may be a bit in a more general control register.
	The 

	Sourcing MD does not reset RD_TRAP; the trap is caused every time MD
	is sourced until RD_TRAP is cleared.  If MD is never sourced
	during a period that RD_TRAP is set, the trap is never caused.
	This is so that a higher-priority trap caused at the same time
	as an RD_TRAP trap will complete and then be followed by the
	RD_TRAP trap.

	If MD is sourced when MD and the RD_TRAP bit are not valid,
	the machine is frozen in the MD source cycle until they are valid.
	

WR_TRAP:
	Set after starting a memory write, after md-start-write or
	vma-start-write, if the cycle wants to cause a page-fault
	or GC trap.  The trap is caused as soon as this bit is set.