author :  Keith Ball
      file   :  /dsgn/interrupts.text
      date   :  23-Feb-1983

      Interrupt routine chaining for the level 1 interrupt.


            The 68000 has 7 auto-vector interrupts.  The Concept
      has allocated these auto-vectors for use by system I/O
      devices and the I/O slots.  The level 1 vector, the lowest
      priority, is used for several interrupting sources.  These
      devices are the DataCom control lines, read in VIA Port A,
      and the NMI and IRQ interrupts from the system I/O slots.
      NMI and IRQ interrupts are the names of the interrupt
      signals from the I/O slots and they do not specify how
      these signals are used on the Concept.

            Since a single vector is used for 5 different
      interrupting sources some mechanism is necessary to allow
      multiple interrupt routines to be invoked when a level 1
      interrupt occurs.  The Concept uses a simple mechanism
      called "chaining".  Chaining allows many interrupt routines
      to share the level 1 interrupt vector.  After each performs
      its necessary interrupt processing, it invokes the next
      routine in the chain.  These succesive invocations
      terminate when the ROM interrupt routine is invoked.  The
      ROM code turns off the DataCom control interrupt and
      performs an RTE.

            To install an interrupt routine at the beginning of
      the chain, the new code first saves the address found in
      the level 1 auto-vector at address $64 in its local data
      space.  This is the address of the routine which is
      currrently at the beginning of the chain.  Next, it places
      the address of the entry point to its interrupt routine in
      the auto-vector location.  The routine will now be invoked
      whenever a level 1 interrupt occurs.  Of course, while any
      operations are performed on the level 1 auto-vector the
      level 1 interrupts must be disabled.

            When the level 1 interrupt occurs the routine is
      invoked, either directly by the processor or through a
      chain call.  The routine performs its necessary interrupt
      processing and then jumps to the routine at the saved
      address.  It should not perform a subroutine call because
      the ROM routine guaranteed to be the last in the chain
      always performs the RTE and does not return to its caller.

              The interrupt routine must always determine if an
      interrupt from the device it handles did occur.  Whether or
      not its device caused the interrupt the routine must call
      the next routine in the chain.  To determine if a slot NMI
      or IRQ caused the interrupt, the routine must check the
      Slot Status register at address $30A01.  For a routine to
      determine if the DataCom control caused the interrupt it is
      necessary that it keeps a "shadow" copy of the VIA Port A
      register and compare the shadow with the actual register to
      see if any bits have changed.

            If the interrupt routine is handling interrupts for a
      slot peripheral, it is necessary for the routine to turn
      off the interrupt at its source, the card in the slot.
      However, if the routine is handling the DataCom control
      lines it should not turn off its interrupting source by
      toggling the IOX line in the VIA Port A.  The ROM interrupt
      routine toggles IOX before it executes the RTE.

            The level 1 interrupt is generated by the hardware
      whenever an odd number of NMI, IRQ, or DataCom control
      lines change their state.  If an even number of them change
      simultaneously then NO interrupt will occur.  To handle
      this contingency a special timer user service routine could
      be written to toggle the IOX line in VIA Port A every so
      often, say 200 milliseconds.  Changing the IOX line will
      generate a level 1 interrupt and allow the interrupt
      routines to check for a state change of their interrupting
      devices.

            This simple chaining mechanism does not allow a
      routine to be removed from the chain unless the routines
      previous to it in the chain have been removed.  If a
      routine is at the top of the chain, therfore it is directly
      invoked by the processor, it may be removed from the chain
      by replacing the saved entry point address of the next
      interrupt routine in the level 1 auto-vector.