TRASH'M-One S:TRASH'M-One16.Pref Linker Error Not Enough Memory Warning this is not an action for kids. OFFSET> SECTION> The Label Found Is: ›17H--- TRASH'M-One V1.6 MC68000 Macro Assembler --- ›18HOriginal coding by Rune Gram-Madsen (ASM-One) ›21HTrashed by Deftronic of Crionics in 1992 ›23HRelease date 25-12-1992 by Deftronic TRASH'M-One By Deftronic Source » timer.device Include : " " Incbin : " " Inclink : " " Inciff : " " Incspr : " " ›52H = File length = (=$ File location = Name : Blks Free Blks Used -dir- FILENAME> DIRNAME> > BEG> END> DEST> DATA> AMPLITUDE> MULTIPLIER> HALF CORRECTION (Y/N)> ROUND CORRECTION (Y/N)> YOFFSET> SIZE (B/W/L)> AMOUNT> BREAKPOINT> RAM PTR> DISK PTR> LENGTH> Sure? EXTEND LABELS WITH> Error creating directory Directory created Sinus created. Couldn't open mathffp.library Couldn't open mathtrans.library mathffp.library mathtrans.library Source not saved !! Continue? File already exists !! Continue ? Exit or Restart (Y/N or R)? ON OFF EOP Remove unused labels (Y/N)? Updating .. Sorting relo-area.. Writing hunk data.. Writing hunk length.. Memory overflow !!! NL -- L7 -- RS -- Mode : Req.Library not found !!! ** Break Pass 1.. Pass 2.. Page Of No Errors Errors Occured !! ReAssembling.. Option O: Optimizing.. NOT Equal Areas ** Warning: Not Found Branch Forced to Word Size D0: A0: SSP= USP= SR= T1 -- SI -- PL= XNZVC PC= PC= ›1;69HD0: ›2;69HD1: ›3;69HD2: ›4;69HD3: ›5;69HD4: ›6;69HD5: ›7;69HD6: ›8;69HD7: ›9;69HA0: ›10;69HA1: ›11;69HA2: ›12;69HA3: ›13;69HA4: ›14;69HA5: ›15;69HA6: ›16;69HA7: ›17;69HSSP= ›18;69HUSP= ›19;69HSR= PL= ›20;69H T1 -- SI -- XNZVC›21;69HPC = Worksp Source L-Ptrs Label Debug Code Reloc IncMem -------- -------- --- Memory directory --- -- Symbol table -- -- Macro -- -- X-Ref -- -- Equ-R -- -- Reg -- ›23;1H Line: Col: Bytes: Free Memory: ----- Time: : : - ›30;1H DC.B DC.W DC.L LB_ Search for: Replace with: Exchange with: Exchange (Y/N/L/G)? SIZE (B/W/L) Jump to line: Steps: Address: Watch: Address not found !! End of program reached !! Watch type (A)scii (S)tring (H)ex (D)ecimal (B)inary Bit(M)ap (P)ointer: Pointer to (A)scii (S)tring (H)ex (D)ecimal (B)inary Bit(M)ap: Pointer type (1) DC.L (2) DC.W (3) DR.L (4) DR.W : Register: Replace (Y/N/L/G)? Jumping.. Buffer Full !! Extern.. Done Registers used: NONE Searching.. Top of text.. Bottom of text.. Create macro.. Mark location and press Macro buffer full !! EXTERN€;; TRASH'M-One Requester.. ** External Level 7 Break ** Bus Error ** Address Error ** Illegal Instruction ** Division By Zero ** CHK exception ** TRAPV ** Privilege Violation ** Trace Trap ** LineA Emulator ** LineF Emulator ** Exception $ Raised At $ Accessing $ Type Instruction $ Length (Modulo): Workspace Memory full Address Reg. Byte/Logic Address Reg. Expected Comma expected Data reg. expected Double Symbol Unexpected End of File User made FAIL Illegal Command Illegal Address size Illegal Operand Illegal Operator Illegal Operator in BSS area Illegal Order Illegal reg. size Illegal Section type Illegal Size Illegal macro def. Immediate operand ex. Include Jam Macro overflow Invalid Addressing Mode LOAD without ORG Missing Quote Conditional overflow NO operand space allowed NOT a constant/label Not in macro Out of Range 0 bit Out of Range 3 bit Out of Range 4 bit Out of Range 8 bit Out of Range 16 bit Relative Mode Error Reserved Word Right parenthes Expected Section overflow String expected Undefined Symbol Register expected Word at Odd Address Not local area Code moved during pass 2 Bcc.B out of range in Macro Out of range (20 to 100) Out of range (60 to 132) Include overflow Linker limitation Repeat overflow Not in Repeat area Double definition Relocation made to EMPTY section File Error No Files No Object No File Space Printer Device Missing Not done Illegal Path Illegal Device Write Protected No disk in drive Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ~ Bit Use ---- --------------------------------------------------------- ~ Unused CUSTOM REGISTERS * -------------------------------------------------------------------------- * ER = EARLY READ : R = READ : W = WRITE : S = STROBE : ? UNKNOWN * -------------------------------------------------------------------------- * 000 ER BLTDDAT 002 R DMACONR 004 R VPOSR 006 R VHPOSR 008 ER DSKDATR 00A R JOY0DAT 00C R JOY1DAT 00E R CLXDAT 010 R ADKCONR 012 R POT0DAT 014 R POT1DAT 016 R POTINP 018 R SERDATR 01A R DSKBYTR 01C R INTENAR 01E R INTREQR 020 W DSKPTH 022 W DSKPTL 024 W DSKLEN 026 W DSKDAT 028 W REFPTR 02A W VPOSW 02C W VHPOSW 02E W COPCON 030 W SERDAT 032 W SERPER 034 W POTGO 036 W JOYTEST 038 S STREQU 03A S STRVBL 03C S STRHOR 03E S STRLONG 040 W BLTCON0 042 W BLTCON1 044 W BLTAFWM 046 W BLTALWM 048 W BLTCPTH 04A W BLTCPTL 04C W BLTBPTH 04E W BLTBPTL 050 W BLTAPTH 052 W BLTAPTL 054 W BLTDPTH 056 W BLTDPTL 058 W BLTSIZE 05A ? BLTCON01 ECS 05C ? BLTSIZV ECS 05E ? BLTSIZH ECS 060 W BLTCMOD 062 W BLTBMOD 064 W BLTAMOD 066 W BLTDMOD 068 UNUSED 06A UNUSED 06C UNUSED 06E UNUSED 070 W BLTCDAT 072 W BLTBDAT 074 W BLTADAT 076 UNUSED 078 ? SPRHDAT ECS 07A UNUSED 07C ? DENISEID ECS 07E W DSKSYNC 080 W COP1LCH 082 W COP1LCL 084 W COP2LCH 086 W COP2LCL 088 W COPJMP1 08A W COPJMP2 08C W COPINS 08E W DIWSTRT 090 W DIWSTOP 092 W DDFSTRT 094 W DDFSTOP 096 W DMACON 098 W CLXCON 09A W INTENA 09C W INTREQ 09E W ADKCON 0A0 W AUD0PTH 0A2 W AUD0PTL 0A4 W AUD0LEN 0A6 W AUD0PER 0A8 W AUD0VOL 0AA W AUD0DAT 0AC UNUSED 0AE UNUSED 0B0 W AUD1PTH 0B2 W AUD1PTL 0B4 W AUD1LEN 0B6 W AUD1PER 0B8 W AUD1VOL 0BA W AUD1DAT 0BC UNUSED 0BE UNUSED 0C0 W AUD2PTH 0C2 W AUD2PTL 0C4 W AUD2LEN 0C6 W AUD2PER 0C8 W AUD2VOL 0CA W AUD2DAT 0CC UNUSED 0CE UNUSED 0D0 W AUD3PTH 0D2 W AUD3PTL 0D4 W AUD3LEN 0D6 W AUD3PER 0D8 W AUD3VOL 0DA W AUD3DAT 0DC UNUSED 0DE UNUSED 0E0 W BPL0PTH 0E2 W BPL0PTL 0E4 W BPL1PTH 0E6 W BPL1PTL 0E8 W BPL2PTH 0EA W BPL2PTL 0EC W BPL3PTH 0EE W BPL3PTL 0F0 W BPL4PTH 0F2 W BPL4PTL 0F4 W BPL5PTH 0F6 W BPL5PTL 0F8 UNUSED 0FA UNUSED 0FC UNUSED 0FE UNUSED 100 W BPLCON0 102 W BPLCON1 104 W BPLCON2 106 ? BPLCON3 ECS 108 W BPL1MOD 10A W BPL2MOD 10C UNUSED 10E UNUSED 110 W BPL0DAT 112 W BPL1DAT 114 W BPL2DAT 116 W BPL3DAT 118 W BPL4DAT 11A W BPL5DAT 11C UNUSED 11E UNUSED 120 W SPR0PTH 122 W SPR0PTL 124 W SPR1PTH 126 W SPR1PTL 128 W SPR2PTH 12A W SPR2PTL 12C W SPR3PTH 12E W SPR3PTL 130 W SPR4PTH 132 W SPR4PTL 134 W SPR5PTH 136 W SPR5PTL 138 W SPR6PTH 13A W SPR6PTL 13C W SPR7PTH 13E W SPR7PTL 140 W SPR0POS 142 W SPR0CTL 144 W SPR0DATA 146 W SPR0DATB 148 W SPR1POS 14A W SPR1CTL 14C W SPR1DATA 14E W SPR1DATB 150 W SPR2POS 152 W SPR2CTL 154 W SPR2DATA 156 W SPR2DATB 158 W SPR3POS 15A W SPR3CTL 15C W SPR3DATA 15E W SPR3DATB 160 W SPR4POS 162 W SPR4CTL 164 W SPR4DATA 166 W SPR4DATB 168 W SPR5POS 16A W SPR5CTL 16C W SPR5DATA 16E W SPR5DATB 170 W SPR6POS 172 W SPR6CTL 174 W SPR6DATA 176 W SPR6DATB 178 W SPR7POS 17A W SPR7CTL 17C W SPR7DATA 17E W SPR7DATB 180 W COLOR00 182 W COLOR01 184 W COLOR02 186 W COLOR03 188 W COLOR04 18A W COLOR05 18C W COLOR06 18E W COLOR07 190 W COLOR08 192 W COLOR09 194 W COLOR10 196 W COLOR11 198 W COLOR12 19A W COLOR13 19C W COLOR14 19E W COLOR15 1A0 W COLOR16 1A2 W COLOR17 1A4 W COLOR18 1A6 W COLOR19 1A8 W COLOR20 1AA W COLOR21 1AC W COLOR22 1AE W COLOR23 1B0 W COLOR24 1B2 W COLOR25 1B4 W COLOR26 1B6 W COLOR27 1B8 W COLOR28 1BA W COLOR29 1BC W COLOR30 1BE W COLOR31 1C0 ? HTOTAL ECS 1C2 ? HSSTOP ECS 1C4 ? HBSTRT ECS 1C6 ? HBSTOP ECS 1C8 ? VTOTAL ECS 1CA ? VSSTOP ECS 1CC ? VBSTRT ECS 1CE ? VBSTOP ECS 1D0 ? SPRHSTRT ECS 1D2 ? SPRHSTOP ECS 1D4 ? BPLHSTRT ECS 1D6 ? BPLHSTOP ECS 1D8 ? HHPOSW ECS 1DA ? HHPOSR ECS 1DC ? BEAMCON0 ECS 1DE ? HSSTRT ECS 1E0 ? VSSTRT ECS 1E2 ? HCENTER ECS 1E4 ? DIWHIGH ECS 1E6 ? BPLHMOD ECS 1E8 ? SPRHPTH ECS 1EA ? SPRHPTL ECS 1EC ? BPL1HPTH ECS 1EE ? BPL1HPTL ECS 1F0 UNUSED 1F2 UNUSED 1F4 UNUSED 1F6 UNUSED 1F8 UNUSED 1FA UNUSED 1FC UNUSED 1FE RW NO-OP(NULL) * -------------------------------------------------------------------------- * 010/09e Audio, Disk, Control | 15 SET/CLR Set/clear control bit. determines if bits written with a 1 get set or cleared. Bits written with zero are always unchanged. 14-13 PRECOMP 1-0 CODE PRECOMP VALUE ---- ------------- 00 none 01 140 ns 10 280 ns 11 560 ns 12 MFMPREC (1=MFM precomp 0=GCR precomp) 11 UARTBRK Forces a UART break (clears TXD) if true. 10 WORDSYNC Enables disk read synchronizing on a word equal to DISK SYNC CODE, located in address dff(07e) 09 MSBSYNC Enables disk read synchronizing on the MSB (most signif bit). Apple type GCR. 08 FAST Disk data clock rate control 1=fast(2us MFM) 0=slow (MFM or GCR) 07 USE3PN Use audio ch 3 to modulate nothing 06 USE2P3 Use audio ch 2 to modulate period of ch 3 05 USE1P2 Use audio ch 1 to modulate period of ch 2 04 USE0P1 Use audio ch 0 to modulate period of ch 1 03 USE3VN Use audio ch 3 to modulate nothing 02 USE2V3 Use audio ch 2 to modulate volume of ch 3 01 USE1V2 Use audio ch 1 to modulate volume of ch 2 00 USE0V1 Use audio ch 0 to modulate volume of ch 1 ~ 0A0/0A2/0B0/0B2/0C0/0C2/0D0/0D2 Audio channel location This pair of registers contains 18 bit starting address of audio channel x DMA data. This is not a pointer register and therefore needs to be reloaded only if a different memory location is to be outputted. ~ 0A4/0B4/0C4/0D4 Audio channel length This register contains the length (number of words) of audio channel x DMA data. ~ 0A6/0B6/0C6/0D6 Audio channel Period This register contains the period (rate) of audio channel x DMA data transfer. The minimum period is 124 color clocks. This means that the smallest number that should be placed in this register is 124 decimal. This corresponds to a maximum sample frequency of 28.86 khz. ~ 0A8/0B8/0C8/0D8 Audio channel Volume This register contains the volume setting for audio channel x. Bits 6,5,4,3,2,1,0 specify 65 linear volume levels as shown below. | 15-07 Not Used 06 Forces Volume to Max (64 ones, no zeros) 05-00 set one of 64 levels (%000000=no output) ~ 0AA/0BA/0CA/0DA Audio channel Data This register is the audio channel DMA data buffer. It contains 2 bytes of data that are 2's complement and are outputted sequentially (with digital-to-analog conversion) to the audio output pins. (LSB = 3 MV) The DMA controller automatically transfers data to this register from RAM. The processor can also write directly to this register. When the DMA data is finished (words outputted=length) and the data in this register has been used, an audio channel interrupt request is set. ~ 048/04A Blitter Pointer C This register contains a pointer to the source C of the blitter. ~ 04C/04E Blitter Pointer B This register contains a pointer to the source B of the blitter. ~ 050/052 Blitter Pointer A This register contains a pointer to the source A of the blitter. ~ 054/056 Blitter Pointer D This register contains a pointer to the destination D of the blitter. ~ 060 Blitter Modulo C A modulo is a number that is automatically added to the address at the end of each line. ~ 062 Blitter Modulo B A modulo is a number that is automatically added to the address at the end of each line. ~ 064 Blitter Modulo A A modulo is a number that is automatically added to the address at the end of each line. ~ 066 Blitter Modulo D A modulo is a number that is automatically added to the address at the end of each line. ~ 044 Blitter first-word mask for source A these patterns in these two registers are ANDed with the first word of each line of data from source A into blitter. ~ 046 Blitter last-word mask for source A these patterns in these two registers are ANDed with the last word of each line of data from source A into blitter. ~ 070 Blitter Data for Source C ~ 072 Blitter Data for Source B ~ 074 Blitter Data for Source A ~ 000 Blitter Data from Destination D ~ 040/042 Blitter control register Area mode Line Mode BIT BLTCON0 BLTCON1 BLTCON0 BLTCON1 15 ASH3 BSH3 START3 TEXTURE3 14 ASH2 BSH2 START2 TEXTURE2 13 ASH1 BSH1 START1 TEXTURE1 12 ASA0 BSH0 START0 TEXTURE0 11 USEA - - - 10 USEB - 0 0 09 USEC - 1 0 08 USED - 1 0 07 LF7 - LF7 0 06 LF6 - LF6 SIGN 05 LF5 - LF5 0 04 LF4 EFE LF4 SUD 03 LF3 IFE LF3 SUL 02 LF2 FCI LF2 AUL 01 LF1 DESC LF1 SING 00 LF0 LINE(0) LF0 LINE(1) ASH 3-0 Shift value of A source BSH 3-0 Shift value of B source USEA use source A USEB use source B USEC use source C USED use destination DLF 7-0 Logic minterms EFE Exclusive fill IFE Inclusive fill FCI Fill carry input DESC Descending control bit LINE Line mode START 3-0 Starting point SIGN Sign flag SING Single bit SUD Up or down bit SUL Up or left bit AUL Always up or left ~ 058 Blitter Size ; H9 H8 H7 H6 H5 H4 H3 H2 H1 H0 W5 W4 W3 W2 W1 W0 H=Hight (1024 Lines Max) W=Width in words (64 words=1024 pixels) Writing this register starts the Blitter ~ 0E0-0F6 Bit Plane Pointer This pair of registers contains the 18-bit pointer to the address of bit-plane x DMA data. These address registers must be initialized by the processor or Copper every vertical blank time. ~ 110-11A Bit Plane Data ~ 108/10A Bit Plane Modulo ~ 100 Bit Plane Control Register 0 | 15 HIRES Hires mode 14 BPU2 13 BPU1 # of bit planes 12 BPU0 11 HOMOD Hold And Modify mode 10 DBLPF Double playfield 09 COLOR Composite video 08 GAUD Genlock audio 07 X 06 X 05 X 04 X 03 LPEN Lightpen 02 LACE Interlace mode 01 ERSY External resync 00 X ~ 102 Bit Plane Control Register 1 | 15 X 14 X 13 X 12 X 11 X 10 X 09 X 08 X 07 PF2H3 06 PF2H2 05 PF2H1 04 PF2H0 03 PF1H3 02 PF1H2 01 PF1H1 00 PF1H0 PF2H=Playfield 2 scroll code PFlH=Playfield 1 scroll code ~ 104 Bit Plane Control Register 2 | 15 X 14 X 13 X 12 X 11 X 10 X 09 X 08 X 07 X 06 PF2PRI 05 PF2P2 04 PF2P1 03 PF2P0 02 PF1P2 01 PF1P1 00 PF1lP0 PF2PR Playfield 2 > 1 PF2P Playfield 2 priority PF1P Playfield 1 priority ~ 098 Collision control | 15 ENSP7 Enable sprite 7/6 14 ENSP5 Enable sprite 5/4 13 ENSP3 Enable sprite 3/2 12 ENSP1 Enable sprite 1/0 11 ENBP6 Enable plane 6 10 ENBP5 Enable plane 5 09 ENBP4 Enable plane 4 08 ENBP3 Enable plane 3 07 ENBP2 Enable plane 2 06 ENBP1 Enable plane 1 05 NVBP6 Match for plane 6 04 MVBP5 Match for plane 5 03 MVBP4 Match for plane 4 02 MVBP3 Match for plane 3 01 MVBP2 Match for plane 2 00 MVBP1 Match for plane 1 ~ 00E Collision detection register | 15 not used 14 Sprite 4 (or 5) to sprite 6 (or 7) 13 Sprite 2 (or 3) to sprite 6 (or 7) 12 Sprite 2 (or 3) to sprite 4 (or 5) 11 Sprite 0 (or 1) to sprite 6 (or 7) 10 Sprite 0 (or 1) to sprite 4 (or 5) 09 Sprite 0 (or 1) to sprite 2 (or 3) 08 Playfield 2 to sprite 6 (or 7) 07 Playfield 2 to sprite 4 (or 5) 06 Playfield 2 to sprite 2 (or 3) 05 Playfield 2 to sprite 0 (or 1) 04 Playfield 1 to sprite 6 (or 7) 03 Playfield 1 to sprite 4 (or 5) 02 Playfield 1 to sprite 2 (or 3) 01 Playfield 1 to sprite 0 (or 1) 00 Playfield 1 to playfield 2 ~ 180-1BE Color Palette ; -- -- -- -- R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 B=Blue, G=Green, R=Red ~ 02E Copper control register This is a 1-bit register that when set true, allows the copper to access the blitter hardware. This bit is cleared by power-on reset, so that the copper cannot access the blitter hardware. | 01 CDANG Copper danger mode. Allows Copper access to blitter if true. ~ 088/08a Copper Restart These addresses are strobe addresses. When written to, they cause the copper to jump indirect using the address contained in the first or second location registers described below. The Copper itself can write to these addresses, causing its own jump indrect. ~ 080/082 Copper first location register ~ 084/086 Copper second location register ~ 08C Copper instruction, dummy ~ 08E/090 Display window start/stop ; V7 V6 V5 V4 V3 V2 V1 V0 H7 H6 H5 H4 H3 H2 H1 H0 ~ 092/094 Display data fetch start/stop ; -- -- -- -- -- -- -- -- H8 H7 H6 H5 H4 H3 -- -- ~ 002/096 DMA control | 15 SET/CLR Set/Clear control bit. Determines if bits Written with a 1 get set or cleared. Bits written with a zero are unchanged. 14 BBUSY Blitter busy status bit (read only) 13 BZERO Blitter logic zero status bit (read only) 12-11 X 10 BLTPRI Blitter DMA priority over CPU (also called "Blitter nasty") 09 DMAEN Enable all DMA below 08 BPLEN Bit Plane DMA Enable 07 COPEN Copper DMA Enable 06 BLTEN Blitter DMA Enable 05 SPREN Sprite DMA Enable 04 DSKEN Disk DMA Enable 03 AUD3EN Audio Channel 3 DMA Enable 02 AUD2EN Audio Channel 2 DMA Enable 01 AUD1EN Audio Channel 1 DMA Enable 00 AUD0EN Audio Channel 0 DMA Enable ~ 020/022 Disk Pointer This pair of registers contains the 18-bit address of disk DMA data. These address registers must be initialized by the processor or Copper before disk DMA is enabled. ~ 024 Disk length This register contains the length (number of words) of disk DMA data. It also contains two control bits, a DMA enable bit, and a DMA direction (read/write) bit. | 15 DMAEN Disk DMA enable 14 WRITE Disk write (ram to disk if 1) 13-0 LENGTH Length (# of words) of DMA Data. ~ 01A Disk data byte/status | 15 DSKBYT Byte ready 14 DMAON 1=Diskdma on 13 DISKWRITE 1=Diskwrite on 12 WORDEQUAL 1=Sync found 11-08 X Not used 07-00 DATA Disk byte data ~ 008/026 Disk DMA data buffer ~ 07E Disk Sync register Holds the match code for disk read synchronization. See ADKCON bit 10. ~ 01C/01E/09A/09C Interrupt ENAble/REQuest bits | 15 SET/CLR Set/Clear control bit. Determines if bits Written with a 1 get set or cleared. Bits written with a zero are unchanged. 14 INTEN Master interrupt (ENAble only, no request) 13 EXTER 6 External interrupt 12 DSKSYN 5 Disk sync register (DSKSYNC) matches disk data 11 RBF 5 Serial port receive buffer full 10 AUD3 4 Audio channel 3 block finished 09 AUD2 4 Audio channel 2 block finished 08 AUD1 4 Audio channel 1 block finished 07 AUD0 4 Audio channel 0 block finished 06 BLIT 3 Blitter finished 05 VERTB 3 Start of vertical blank 04 COPER 3 Copper 03 PORTS 2 I/O ports and timers 02 SOFT 1 reserved for software-initiated interrupt 01 DSKBLK 1 Disk block finished 00 TBE 1 Serial port transmit buffer empty ~ 00A/00C Mouse/Joystick counter. ; MDAT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0 ~ 036 Write to all four joystick-mouse counters at once. Mouse counter write test data: ; 0DAT Y7 Y6 Y5 Y4 Y3 Y2 -- -- X7 X6 X5 X4 X3 X2 -- -- 1DAT Y7 Y6 Y5 Y4 Y3 Y2 -- -- X7 X6 X5 X4 X3 X2 -- -- ~ 016/034 Pot Port Data/Start | 15 OUTRY Output enable for paula pin 36 14 DATRY I/O data paula pin 36 13 OUTRX Output enable for paula pin 35 12 DATRX I/O data paula pin 35 11 OUTLY Output enable for paula pin 33 10 DATLY I/O data paula pin 33 09 OUTLX Output enable for paula pin 32 08 DATLX I/O data paula pin 32 07-01 0 Reserved 00 START Start pots ~ 028 Refresh pointer This register is used as a dynamic RAM refresh address generator. It's writeable for test purposes only, and should never be written by the microprocessor. ~ 018/030 Serial port data/status | 15 OVRUN overrun. 14 RBF buffer full 13 TBE buffer empty 12 TSRE shift register empty 11 RXD RXD pin 10 0 Not used 09 STP Stop bit 08 STP-DB8 Stop bit, if long Data bit 07 DB7 Data bit 06 DB6 Data bit 05 DB5 Data bit 04 DB4 Data bit 03 DB3 Data bit 02 DB2 Data bit 01 DB1 Data bit 00 DB0 Data bit ~ 032 Serial port period and control | 15 LONG Defines serial receive as 9-bit word. 14-00 RATE Defines baud rate=1/((N+1)*.2794 microsec.) If the number is N, then the baud rate is 1 bit every (n+1)*.2794 ms. ~ 120-13E Sprite Pointer This pair of registers contains the 18-bit address of sprite x DMA data. These address registers must be initialized by the processor or Copper every vertical blank time. ~ 140/148/150/158/160/168/170/178 Sprite x vert-horiz start position data This register work together with SPRCTL as position, size and feature sprite control registers. They usually loaded by the sprite DMA channel during horizontal blank. However, they may be loaded by either processor or Copper at any time. | 15-08 SV7-SV0 Start vertical value. High bit (SV8) is in SPRxCTL. 07-00 SH8-SH1 Start horizontal value. Low bit (SV8) is in SPRxCTL. ~ 142/14A/152/15A/162/16A/172/17A Sprite x vert stop and control data This register work together with SPRPOS as position, size and feature sprite control registers. They usually loaded by the sprite DMA channel during horizontal blank. However, they may be loaded by either processor or Copper at any time. | 15-08 EV7-EV0 End (Stop) vertical value low 8 bits 07 ATT Sprite attach control bit (odd sprites) 06-03 Not Used 02 SV8 Start vertical value high bit 01 EV8 End (stop) vertical value high bit 00 SH0 Start horizontal value low bit (Writing this address disables sprite horizontal comparator circuit) ~ 144/146/14C/14E/154/156/15C/15E/164/166/16C/16E/174/176/17C/17E Sprite image Data ~ 038 Horizontal sync with VB and EQU ~ 03A Horizontal sync with VB (vertical blank) ~ 03C Horizontal sync ~ 03E Identification of long horizontal line ~ 004/02A Vertical most significant bit (and frame flop) ; LOF -- -- -- -- -- -- -- -- -- -- -- -- -- -- V8 LOF=Long Frame (auto toggle control bit in BPLCON0) ~ 006/02C Vertical and horizontal position of beam or lightpen ; V7 V6 V5 V4 V3 V2 V1 V0 H8 H7 H6 H5 H4 H3 H2 H1 RESOLUTION = 1/160 of screen width (280 ns) ~ 1FE No operation ~ 05A/05C/05E/078/07C/106/1c0/1C2/1c4/1c6/1c8/1ce/1cc/1ce/1d0/1d2/1d4/1d6/1d8/1da/1dc/1de/1e0/1e2/1e4/1e6/1e8/1ea/1ee Sorry no information! (ECS register) t:Swapfile0 t:Swapfile1 t:Swapfile2 t:Swapfile3 t:Swapfile4 t:Swapfile5 t:Swapfile6 t:Swapfile7 t:Swapfile8 t:Swapfile9 ALLOCATE Fast/Chip/Abs> ABSOLUTE Memory Addr.> ADD-WORKSPACE (Max. ) KB> PRT: Project Zap Source ZS Old O Read.. Source R Binary RB Object RO Write.. Source W Binary WB Object WO Link WL Insert I Update U Zap File ZF Zap IncMem ZI Create Dir CD Directory V Preferences.. Rescue Level 7 NumLock AutoAlloc ReqLibrary PrinterDump Interlace 1 Bitplane Source .S Close WB Auto Backup Save Marks Write Preferences.. WP AddWorkMem =M About.. »» TRASH'M-One V1.6 «« Based on ASM-One Send your idea's / bug reports to : Deftronic of Crionics A program worth using is worth Trashing! Exit ! Assembler Assemble.. Assemble Optimize List File Paging Halt Page AllErrors Debug Label: UCase=LCase Comment Ds Clear Assemble % Editor Debugger Monitor Edit Funct. Block.. Mark Copy Cut Insert Fill UnMark LowerCase UpperCase Rotate Registers Write VertFill Search.. Search Forward Replace.. Replace Forward Exchange.. Exchange Forward Del Line Marks.. Mark 1 Mark 2 Mark 3 Mark 4 Mark 5 Mark 6 Mark 7 Mark 8 Mark 9 Jump 1 Jump 2 Jump 3 Jump 4 Jump 5 Jump 6 Jump 7 Jump 8 Jump 9 Jump ;; Jump Line Move.. BOLN shift left EOLN - right PgUp - up PgDn - down Up100 alt Up Down100 - Down Top Bottom Word alt left NWord - right MakeMacro Do Macro Grab Word LineNumbers AutoIndent HoldCursorX Exit esc Debug Funct. Step One (down) Enter (right) Run Step n Edit Regs AddWatch DelWatch... ZapWatch Jump Addr Jump Mark B.P. Addr B.P. Mark Zap all BP Extern DisAssemble ShowSource Exit esc Mon Funct. DisAssem HexDump AsciiDump Jump Addr Last Addr Mark 1 Mark 2 Mark 3 Jump 1 Jump 2 Jump 3 QuickJump Grab Addr Search.. Search Forward OnlyAscii Exit esc Command Editor.. Top T Bottom B Search L Zap Line ZL Print Line P Ext. Labels EL Offset L.F. =L Memory.. Edit M DisAssem D HexDump H Ascii N DisLine @D Assemble @A HexLine @H BinLine @B AsciiLine @N Search S Fill F Copy C Compare Q Sinus CS Insert.. DisAssem ID HexDump IH Binary IB Ascii IN Sinus IS Assemble.. Assemble A Memory @A Optimize AO Debug AD Symbols =S Monitor.. Jump J Go G Step K Status X Zap BPS ZB Disk.. ReadSector RS ReadTrack RT WriteSector WS WriteTrack WT Calc Check CC Extern E Output > Calculate ? CustomRegs =C Read Source Write Source Read Binary Write Binary Read Object Write Object Write Link Write Block Direct Output Zap File Insert Source Yes Restart No Are you SURE ? Exit ? Or Restart ? DELETE Sources on hold ? Request.. LR Sources in memory will be DELETED? ORI.B ORI.W ORI.L ORI.B ORI.W ANDI.B ANDI.W ANDI.L ANDI.B ANDI.W SUBI.B SUBI.W SUBI.L ADDI.B ADDI.W ADDI.L EORI.B EORI.W EORI.L EORI.B EORI.W CMPI.B CMPI.W CMPI.L BTST BCHG BCLR BSET BTST BCHG BCLR BSET MOVEP.W MOVEP.L MOVEP.W MOVEP.L MOVE.B MOVE.L MOVE.W CHK.L CHK.W LEA NEGX.B NEGX.W NEGX.L MOVE CLR.B CLR.W CLR.L MOVE NEG.B NEG.W NEG.L MOVE NOT.B NOT.W NOT.L MOVE BCD LINK.L SWAP PEA MOVEM.W EXT.W MOVEM.L EXT.L TST.B TST.W TST.L ILLEGAL TAS MOVEM.W MOVEM.L LINK.W MOVE.L MOVE.L TRAP UNLK RESET NOP RTE RTR RTS STOP JSR JMP ADDQ.B SUBQ.B ADDQ.W SUBQ.W ADDQ.L SUBQ.L Scc DBcc BRA.z BSR.z Bcc.z OR.B OR.B SBCD.B SBCD.B OR.W OR.W OR.L OR.L DIVU.W DIVS.W SUB.B SUB.B SUBX.B SUBX.B SUB.W SUB.W SUBX.W SUBX.W SUB.L SUB.L SUBX.L SUBX.L SUBA.W SUBA.L LINE_A CMP.B EOR.B CMPM.B CMP.W EOR.W CMPM.W CMP.L EOR.L CMPM.L CMPA.W CMPA.L AND.B AND.B ABCD.B ABCD.B AND.W AND.W EXG EXG AND.L AND.L EXG MULU.W MULS.W ADD.B ADD.B ADDX.B ADDX.B ADD.W ADD.W ADDX.W ADDX.W ADD.L ADD.L ADDX.L ADDX.L ADDA.W ADDA.L ASR.B ASL.B ASR.B ASL.B LSR.B LSL.B LSR.B LSL.B ROR.B ROL.B ROR.B ROL.B ROXR.B ROXL.B ROXR.B ROXL.B ASR.W ASL.W ASR.W ASL.W LSR.W LSL.W LSR.W LSL.W ROR.W ROL.W ROR.W ROL.W ROXR.W ROXL.W ROXR.W ROXL.W ASR.L ASL.L ASR.L ASL.L LSR.L LSL.L LSR.L LSL.L ROR.L ROL.L ROR.L ROL.L ROXR.L ROXL.L ROXR.L ROXL.L ROXR.W ROXL.W ROR.W ROL.W ASR.W ASL.W LSR.W LSL.W LINE_F DC